Abstract

On December 16, 2009, a comprehensive proposal for the development of a Universal Verification Methodology (UVM) was made by Accellera. The goal of the proposal is to create a UVM that combines the best of OVM and VMM as well as other contributions from the industry. The deliverables are a standard verification methodology and common base class library (CBCL) to enable users to deploy an efficient, reusable, and interoperable SystemVerilog verification environment. The first official release of this standard, including the CBCL, is expected very soon.

What does all this really mean to the verification engineer working in the trenches? In this presentation, we offer a pragmatic look at the key aspects of UVM and CBCL. Starting with an overview, we will examine UVM recommendations for developing a constrained-random verification environment, including its architecture and implementation, coverage collection, response-checking, phasing, communication, and synchronization between various components. We will conclude with an example of how to quickly get started with your first UVM Testbench.

Outline

• UVM – At a Glance
  • Background and Motivation
    • History, including the interoperability library
  • Motivating example
    • Example using OVM
    • Example using VMM
    • Example using UVM
• Key Components of UVM
  • Testbench Architecture
  • Creating objects and data objects using factories
  • Core utilities
    • Field Automation
    • Copy/Compare/Packing etc
  • Component Hierarchy creation and configuration
  • Communicating between components using TLM
  • Creating stimuli => Transactions and Sequences
  • Phasing and synchronization
  • Reporting utilities
• Getting Started
  • Downloading UVM Class Library
  • Creating your first Testbench
  • Open Source Community

Abstract

Any ASIC or FPGA design with any degree of sophistication includes multiple interfaces that communicate using numerous protocols such as PCIE, AXI, and Ethernet. Testbenches are responsible for coordinate the flow of sequences of protocol transactions and sending them their associated design interfaces. Some examples of sequence include initialization sequences, opcode sequences, interrupt service routine sequences, background traffic sequence, or perhaps some traffic sequence. Virtual sequencers give testbenches an apparatus that allows for coordinating transaction flow. It allows users to coordinate timing and data between the multiple interfaces.

Although many of today’s verification methodologies such as OVM discuss virtual sequencers, they do not cover the full gamut. This webinar discusses the basics of virtual sequences as well as techniques and issues outside the scope of today’s verification methodologies. Reuse techniques are highlighted throughout the webinar. In addition, the techniques discussed have been successfully utilized in several SoC verification efforts.

This webinar first includes an overview sequences, sequencers, drivers, and sequence libraries. Next, the webinar transitions into a detailed description of virtual sequences and virtual sequencers. After that the webinar discusses a reusable boiler plate virtual sequence that allows coordination of design initialization, interrupt sequences, and traffic pattern sequences. Finally, the webinar presents techniques that allow test writers to have a high degree of controllability using virtual sequences.