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| Date |
Location |
Registration |
| Tuesday, Oct 14, 2008 |
Silicon Valley
Network Meeting Center Map It
Techmart - Santa Clara
5201 Great America Pkwy # 122
Santa Clara, CA 95054
(408) 562-6111
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| Tuesday, Oct 21, 2008 |
Austin
Hyatt Regency Austin Map It
208 Barton Springs Road
Austin, TX 78704
(512) 477-1234
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| Monday, Oct 27, 2008 |
Japan
Shin-Yokohama Kokusai Hotel ( South Bldg. ) Map It
Reserved Room: "Hill Top"
3-18-1 Shin-Yokohama, Kohoku-ku,
Yokohama 222-0033
Tel: +81 45 474-0766
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| Friday, Oct 31, 2008 |
Taiwan
Grand Hyatt Taipei Map It
2, Song Shou Road,
Taipei, Taiwan 11051
Tel: +886 2 2720 1234
Fax: +886 2 2720 1111
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| Monday, Nov 3, 2008 |
Israel
Dan Accadia Herzliya Hotel Map It
Ramot-Yam 122 St.
Herzliya Beach, 46851
Tel: 972-9-9597070
Fax: 972-9-9597090/91
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A1 - Abstract: Requirements Based Verification
Projects aren't successful by accident, and processes are a proven good way of making sure we're doing the right things at the right times, and in the right way. Two of the most important yet frequently ignored processes in verification are requirement extraction and prioritization. Both are essential in defining the work that really needs to be done, yet experience shows that they are seldom attempted with any rigor. Enthusiasm tails off rapidly as soon as the "real work" of coding the testbench becomes feasible, which is a shame, because projects that don't know where they're going tend not to get there... Subsequent verification tends to be inefficient, which is bad for quality and schedule, and can lead to a stressful and unsatisfying project experience for all involved.
In this presentation, an introduction to both of these processes is provided. Attendees will learn why processes are needed, will walk through the major steps involved in using processes, and will tackle some of the common problems faced by teams adopting them for the first time, such as the perception of low personal motivation and benefits, lack of permission, and the all time classic "we don't have time".
This presentation is extracted from Verilab's Requirements Based Verification workshop, and will be of interest to verification engineers and managers who would like to improve the efficiency of their verification efforts.
Highlights
- Verification Processes
- Overview of common processes
- What can happen without processes
- Benefits of having processes
- Adopting RBV
- Discussion of common problems
- Process 1: Requirements Extraction
- Techniques for understanding a design
- Identifying potential faults and failures
- Types of failures, and sources of bugs
- "Brainstorming" - participants, organization, structure & deliverables
- Writing requirements
- Why detail is important
- Process 2: Requirements Prioritization
- Why do we need to prioritize?
- Factors that influence priority
- Techniques for determining influence values
- Techniques for determining priority
A2 - Abstract: Building Flexible and Reusable Testbenches using a Layered
Approach to Stimulus Generation
In the beginning, there were directed tests, and they were good. Chips were verified, project deadlines were met, and high quality chips were taped out. However, as time has progressed chips have become larger and more complex. Traditional test writing approaches, while still valid in many instances, have not scaled well to meet the challenges of new categories of devices built to take advantage of an ever increasing number of transistors on a single chip.
Layering stimulus is an important technique when designing large testbenches and verification IP intended for reuse. Although the fundamental concepts are well known and well practiced in the context of testbench architecture, many people struggle to apply the same techniques to stimulus generation. The e Reuse Methodology formalized the concept of generating stimulus in constrained random testbenches using a layered approach back in 2002. The concept has also been introduced more recently in the VMM and OVM methodology libraries for SystemVerilog.
In this presentation, layered stimulus generation concepts, architecture, and motivation will be described. Potential drawbacks will be identified and tips for a successful layered stimulus generation implementation will be provided.
Highlights
- What is Layered Stimulus Generation
- Advantages of Layered Stimulus Generation
- Typical components of a Layered Stimulus Generation solution
- Layered Stimulus Generation in the VMM and OVM
- Randomization and Layered Stimulus Generation
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