Verification Now - Verification Planning of Complex SoCs for SystemVerilog Testbench Design

SPONSORS

Content developed and presented by:

To sign up for a free subscription to EDN, please click here

Verification Planning of Complex SoCs and Advanced Techniques
for SystemVerilog Testbench Design

Today's complex designs require a well thought out verification strategy. Proper verification planning and the use of advanced techniques in a SystemVerilog environment can help guarantee that your design and testbench verification process will go smoothly.

This technical seminar will provide attendees with information on why verification planning is needed and how to apply it to your methodology effectively. We'll also look at the importance of layered stimulus generation techniques for building flexibility and reusability into your SystemVerilog testbench and how to successfully implement them.

JL Gray on the Seminar Tour

Detailed Abstract of 2008 Seminar Topics

Requirements Based Verification

Building Flexible and Reusable Testbenches using a Layered
Approach to Stimulus Generation

Check Back for Verification Now 2008 Seminars

Verification Now Event Schedule for Japan

Time	Topic
9:30-10:00 a.m	Reception
10:00-10:10 a.m.	Opening
10:15-11:45 a.m.	Requirements Based Verification Presenter: JL Gray, Verilab Highlights Verification Processes Overview of common processes What can happen without processes Benefits of having processes Adopting RBV Discussion of common problems Process 1: Requirements Extraction Techniques for understanding a design Identifying potential faults and failures Types of failures, and sources of bugs "Brainstorming" - participants, organization, structure & deliverables Writing requirements Why detail is important Process 2: Requirements Prioritization Why do we need to prioritize? Factors that influence priority Techniques for determining influence values Techniques for determining priority
11:45-12:45 p.m.	Lunch
12:45-13:15 p.m.	Sponsor presentation
13:15-13:45 p.m.	Sponsor presentation
13:45-14:15 p.m.	Sponsor presentation
14:15-14:30 p.m.	Break
14:30-15:30 p.m.	Building Flexible and Reusable Testbenches using a Layered Approach to Stimulus Generation Presenter: JL Gray, Verilab Highlights What is Layered Stimulus Generation Advantages of Layered Stimulus Generation Typical components of a Layered Stimulus Generation solution Layered Stimulus Generation in the VMM and OVM Randomization and Layered Stimulus Generation
15:30 p.m.	Closing

-->

Home | Locations | Register | Contact